1. Field
The various circuit embodiments described herein relate in general to phase-locked loops (PLLs), and, more specifically, to PLLs and methods for making and using the same in which the loop bandwidth scales with PLL the reference frequency while maintaining a constant damping factor, FREF, without a requirement that the value of the reference frequency, FREF, be known.
2. Background
An example of a typical phase-locked loop circuit (PLL) 10 is shown in FIG. 1, to which reference is now made. The PLL 10 has a digital phase-frequency detector (DPFD) 12, herein sometimes referred to as a “phase detector,” that receives a reference frequency (FREF) signal on a first input line 14 and a feedback signal on a second input line 16. The DPFD 12 determines whether the phase of the feedback signal leads or lags the phase of the reference frequency, FREF, to command either an up or down signal on output lines 18 and 20, respectively. The up command, for example, indicates that the phase of the feedback signal leads the phase of the reference frequency, FREF, and the down command indicates that the phase of the feedback signal lags the phase of the reference frequency, FREF.
The signal on the up output line 18 controls a switch 22 to apply current from a first current source 24 to an integrator 26 to increase the voltage on the input 27 of the transconductance amplifier 28. The signal on the down output line 20 controls a switch 30 to sink current through a second current source 32 from the integrator 26 to a reference potential, or ground, to decrease the voltage on the input of the transconductance amplifier 28. The integrator 26 has a first capacitor 34 between the input 27 to the transconductance amplifier 28 and a reference potential or ground. In addition, the integrator 26 has a resistor 36 and a second capacitor 38 in series between the input to the transconductance amplifier 28 and the reference potential, or ground.
The transconductance amplifier 28 produces an output current, IVCO, on line 40 to control the frequency of a voltage-controlled oscillator (VCO) 42. The VCO 42 produces a base output frequency on line 44 that is proportional to the input voltage to the transconductance amplifier 28, which, as described above, is proportional to the amount of lead or lag of the phase of the feedback voltage on line 16 with respect to the reference frequency, FREF. The base output frequency from the VCO 42 on line may be divided by a number, for example QDIV, by a frequency divider 46 to provide a PLL frequency output, FOUT, on output line 48. The base frequency output from the VCO 42 on line 44 may also be divided by a number, for example, MDIV, to provide a frequency output on feedback line 16 to the second input of the DPFD 12 for comparison with the reference frequency, FREF. The base frequency output from the VCO 42 can also be feedback to the DPFD 12 by another means to make a comparison with the reference frequency, FREF.
One of the problems, however, especially for a chip manufacturer, is that often the value of the reference frequency, FREF, that customers may employ in the operation of the PLL is not known. Consequently, the design of a single PLL that is suitable for diverse purposes can be very difficult. Moreover, PLLs are often designed to operate over a large reference frequency range. For example in some applications, the reference frequency, FREF, may be anywhere in a range between 2 MHz and 30 MHz.
This can be appreciated from an analysis of the loop behavior of the circuit 10 of FIG. 1, which can be modeled by the phase-domain model 50 of FIG. 2, to which reference is now additionally made. In the phase-domain model 50 of FIG. 2, the phase of the input signal, φREF, is applied on line 52 to an adder 54, the output of which is applied to a loop filter 56. The loop filter 56 models the transistor level response of the feedback loop of the circuit 10 of FIG. 1. The output of the loop filter 56 is applied to a transconductance amplifier 58, which produces an output that is applied to an integrating capacitor 60 and to a delay block 62. The transconductance amplifier 58 along with the integrating capacitor 60 models the behavior of the transconductor circuit 28, VCO 42, and feedback divider 47 of FIG. 1. The delay supplied by the delay block models the sample and hold delay of the DPFD 12, which in the example illustrated is chosen to be equal to 0.6 times the time period of the FREF signal. The output of the delay block 62 is subtracted in the adder 54 from the input phase reference signal, φREF, on line 52. To complete the model of the loop behavior, KVCO is simulated from the given oscillator architecture.
FIG. 3, to which reference is now additionally made, is a graph of closed loop gain in dB verses frequency for two input reference frequencies of 2 megahertz and 30 megahertz. Thus, for a range of reference frequencies, FREFs, between 2 MHz and 30 MHz (the actual value being unknown)+NDIV (the actual value being unknown) the following issues occur.
A typical PLL is designed with a loop-bandwidth of less than FREF/10 in order to get a stable response from the PLL across all process and voltage corners. Higher loop-bandwidth translates to faster settling time for the PLL 10. However, the absolute value of the bandwidth can be chosen based on the particular application in which the PLL is used. The zero 66 of the loop-filter which is formed by resistor 36 and capacitor 38 is usually chosen to be a factor 1/K1 of the loop-bandwidth. The absolute value of the factor 1/K1 can change with the intended application. As an example, in this embodiment the factor is set at K1=3, so zero 66 is parked near 66 KHz. The pole 68, which is formed by resistor 36 and the series combination of capacitor 34 and capacitor 38, is usually chosen to be a factor K2 of the loop-bandwidth. In this embodiment the value of K2 is chosen to be 3 so pole 68 is set at 600 KHz.
With the above combination of loop-filter pole and zero, the bandwidth comes close to desired value of 200 KHz as shown by curve 67 of FIG. 3. The value of the charge-pump is chosen in conjunction of loop-gain such that the loop is stable and loop-peaking is met for the application. Now if a traditional PLL, which is designed for FREF=2 MHz and output of 400 MHz, is used with input FREF=30 MHz, then it does not work, because for 30 MHz PLL, the desired loop-bandwidth would be 3 MHz and in that case both designed zero 66 and pole 68 will come inside the loop-bandwidth as shown in FIG. 4. As a result the PLL loop frequency response becomes the curve 72 shown in FIG. 3 which has over 20 dB of peaking. This implies that system has gone unstable.
Another challenge is that it is desirable for the output frequency, FOUT, be in a range between 100 MHz and 500 MHz. The applicable formulae are:
      LG    =                            I          CP                ⁢                  K          v                ⁢                  K          LPF                    M                  ω      n        =                                        I            CP                    ⁢                      K            v                                    MC          1                          ζ    =                  1        2            ⁢                                                  I              CP                        ⁢                          K              v                        ⁢                          C              1                                M                    ⁢              R        1                        ω      u        =                            I          CP                ⁢                  K          v                ⁢                  R          1                    M      where:    LG is the loop gain    ICP is the charge-pump current    Kv is the gain of the VCO 42    KLPF is the response of the loop low-pass filter 56    M is the frequency divisor in the feedback loop    ωn is the natural frequency of the loop    C1 is the capacitance of the loop zero capacitor 60    ζ is the loop damping factor    R1 is the resistance of the loop zero resistor 36    ωu is the frequency of the unity gain cross-over point
For the case where the loop frequency, FREF, is 2 MHz, the loop bandwidth is 200 KHz, and the zero is at 50 KHz, the charge-pump current, ICP, is chosen so that the damping factor, ζ, is approximately 1 for an output frequency, FOUT, of 400 MHz. This can be seen in the graph of loop gain verses frequency of FIG. 5, to which reference is now additionally made. The curve 80 shows the 400 MHz frequency response and curve 82 shows a 100 MHz frequency response. Over an output frequency range between 100 MHz and 500 MHz, with ICP held constant and MDIV varying from 50 to 250, it can be seen that the loop gain has an increase factor of five, and is only marginally stable. Thus, even though the reference frequency, FREF, may be known, loop may become unstable. Therefore, in order to maintain loop stability, the traditional approach requires the user to specify information about the reference frequency, FREF, to enable the charge-pump current, ICP, to be scaled with respect to the frequency divider, MDIV.
Nevertheless, even though a reference frequency, FREF, may be specified, as a practical matter, most PLL designs are optimized for only a few reference frequencies, FREFs. For other reference frequencies, FREFs, the damping factor, ζ, may still change. Changes in the damping factor, ζ, may cause overshoot and stress the device.
What is needed, therefore, is a PLL and method for making and using it in which the loop bandwidth scales with the reference frequency, FREF, whereby it is not necessary to actually know the reference frequency, FREF. Also needed is an autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency.